Design and Tuning of a Modified Power-Based PLL for Single-Phase Grid-Connected Power Conditioning Systems

One of the most important aspects for the proper operation of the single-phase grid-tied power-conditioning systems is the synchronization with the utility grid. Among various synchronization techniques, phase locked loop (PLL)-based algorithms have found a lot of interest for the advantages they present. Typically, the single-phase PLLs use a sinusoidal multiplier as the phase detector (PD). These PLLs are generally referred to as the power-based PLL (pPLL). In this paper, the drawbacks associated with the pPLL technique (i.e., the sensitivity to the grid voltage variations, and the double-frequency oscillations that appear in the estimated phase/frequency) are discussed in detail, and some of the previously reported solutions are examined. Then, to overcome these drawbacks, a simple and effective technique, called the double-frequency and amplitude compensation (DFAC) method is proposed. The effectiveness of the proposed method is evaluated through a detailed mathematical analysis. A systematic design method to fine-tune the PLL parameters is then suggested, which guarantees a fast transient response, a high disturbance rejection capability, and a robust performance. Finally, the simulation and experimental results are presented, which highlight the effectiveness of the proposed PLL.