Title :
Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells
Author :
Woongrae Kim ; Milor, Linda
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
In this paper we present a Built-In Self Test (BIST) methodology for diagnosis of backend time-dependent dielectric breakdown (BTDDB), via voiding due to electromigration (EM), and stress-induced voiding (SIV) in SRAM cells. Our built-in self test methodology consists of two test procedures. First, faulty cells suffering from wearout mechanisms in the SRAM system are isolated. Then, these faulty cells are tested to determine the cause of wearout.
Keywords :
SRAM chips; built-in self test; electric breakdown; electromigration; BIST; BTDDB; SIV; SRAM cells; backend time-dependent dielectric breakdown; backend wearout mechanisms; built-in self test methodology; electromigration; stress-induced voiding; Built-in self-test; Circuit faults; Leakage currents; Logic gates; Resistance; SRAM cells; Backend TDDB; Built-In Self Test; Electromigration; Reliability; Stress Induced Voiding;
Conference_Titel :
VLSI Test Symposium (VTS), 2014 IEEE 32nd
Conference_Location :
Napa, CA
DOI :
10.1109/VTS.2014.6818746
