DocumentCode
142029
Title
Structural Software-Based Self-Test of Network-on-Chip
Author
Dalirsani, Atefe ; Imhof, Michael E. ; Wunderlich, H.-J.
Author_Institution
Inst. of Comput. Archit. & Comput. Eng., Univ. of Stuttgart, Stuttgart, Germany
fYear
2014
fDate
13-17 April 2014
Firstpage
1
Lastpage
6
Abstract
Software-Based Self-Test (SBST) is extended to the switches of complex Network-on-Chips (NoC). Test patterns for structural faults are turned into valid packets by using satisfiability (SAT) solvers. The test technique provides a high fault coverage for both manufacturing test and online test.
Keywords
computability; integrated circuit testing; network-on-chip; NoC; SAT solvers; SBST; manufacturing test; network-on-chip; online test; satisfiability solvers; software-based self-test; structural faults; test patterns; Automatic test pattern generation; Built-in self-test; Circuit faults; Integrated circuit modeling; Logic gates; Mathematical model; Automatic Test Pattern Generation (ATPG); Boolean Satisfiability (SAT); Network-on-Chip (NoC); Software-Based Self-Test (SBST);
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium (VTS), 2014 IEEE 32nd
Conference_Location
Napa, CA
Type
conf
DOI
10.1109/VTS.2014.6818754
Filename
6818754
Link To Document