Test generation and design-for-testability for flow-based mVLSI microfluidic biochips

Advances in flow-based microfluidic biochips offer tremendous potential for biochemical analyses and clinical diagnostics. However, the adoption of flow-based biochips is hampered by defects that are especially common for chips fabricated using soft lithography techniques. Recently published work on fault detection in flow-based biochips is based on logic-circuit modeling of the microfluidic channels and control valves, followed by classical test generation for digital circuits. However, this approach is not applicable to realistic designs because the circuit model is generated manually and many real defects are mapped to undetectable faults in the logic-circuit model. We present a technique for automated and hierarchical generation of the logic-circuit model from the layout of a flow-based microfluidic chip. Moreover, based on the analysis of untestable faults in the logic-circuit model, we present a design-for-testability (DfT) technique that can achieve 100% fault coverage. Two microfluidic VLSI (mVLSI) chips, each containing over 1500 valves, are used to demonstrate the automated model generation and DfT solutions.