Low power VLSI architectures for one bit transformation based fast motion estimation

In the present paper, architectures implementing fixed block size and variable block size (VBS) motion estimation (ME) algorithms on one bit transformed (1-BT) image frames have been presented. The proposed architectures perform ME by applying diamond search (DS) algorithm on 1-BT image frames. The 1-BT based ME is usually performed by applying full search (FS) algorithm. Our simulation results reveal that the application of DS on 1-BT based ME can significantly reduce the computational complexity which is observed in FS based 1-BT ME at a tolerable degradation in the quality. In terms of latency, the architectures have been shown to be superior to several other 1-BT ME architectures. The presented DS based 1-BT ME architectures have succeeded in reducing the minimum clock frequency required to process a video sequence with a given frame size and frame rate, which in turn reduces the overall power consumption compared with other ME architectures. In particular, for processing SDTV sequences (1280×720 @ 30 fps), the power consumption by the proposed VBS ME architecture is reduced by at least 41% compared to the other 1-BT based ME architectures available in literature. The proposed architectures are therefore, considered suitable for low-power portable video applications typically operated by battery power.