DocumentCode
142044
Title
Design for data-center, low-power and SoCs
Author
Paul, Rick ; Khan, Aurangzeb
Author_Institution
Cisco Systems
fYear
2014
fDate
15-17 Sept. 2014
Firstpage
1
Lastpage
1
Abstract
Today´s design problems in SoC have moved away from being simply providing faster clock rates and higher transistor counts towards providing more data bandwidth and managing increases in power consumption and growing thermal challenges. The eight papers in this section will examine various approaches to address these requirements.
Keywords
CMOS integrated circuits; Clocks; Computer architecture; Flip-flops; Manufacturing; Performance evaluation; System-on-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
Conference_Location
San Jose, CA, USA
Type
conf
DOI
10.1109/CICC.2014.6946106
Filename
6946106
Link To Document