Modeling location based wafer die yield variation in estimating 3D stacked IC yield from wafer to wafer stacking

3D-Stacked ICs manufactured from wafer to wafer stacking are known to suffer from significant yield degradation from the compounding of the defect probabilities for individual dies. However, recent experiments, based on carefully simulated wafer defect maps and validated by silicon data, have shown that traditional yield estimates for 3D-SICs that assume uniform defect probabilities across the stacked wafers can be pessimistic by up to 50%. This is due to yield variations at the different die locations on the wafer resulting from the commonly observed clustering of defects, and also from systematic defects introduced by equipment and handling issues during manufacturing. In this paper we present a novel 3D-SIC yield model which for the first time accurately estimates the impact of this location based wafer die yield variation on the 3D-SIC yield. We further develop a simplified compact model that uses the average die yield, and two easy to obtain parameters (a and σ) that capture the essential spatial information needed for accurately estimating the 3D-SIC yields. The new models are extensively validated against both simulated defect maps and actual silicon data. They promise to greatly simplify meaningful study of cost trade-offs while exploring implementation options for 3D-SICs early in the design phase.