DocumentCode :
142062
Title :
Challenges for analog nanoscale technology
Author :
Venkatraman, Ramnath ; Guo, Richard
Author_Institution :
Avago Technologies
fYear :
2014
fDate :
15-17 Sept. 2014
Firstpage :
1
Lastpage :
1
Abstract :
The five papers in this session address various facets of technology scaling for SoCs as determined by the need to achieve power, performance and cost targets, along with meeting ever-increasing functionality requirements without compromising reliability.
Keywords :
Accuracy; Computational efficiency; Layout; Nanoscale devices; Semiconductor device reliability; System-on-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
Conference_Location :
San Jose, CA, USA
Type :
conf
DOI :
10.1109/CICC.2014.6946115
Filename :
6946115
Link To Document :
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