Power/ground supply voltage variation-aware delay test pattern generation

VLSI technology scaling leads to a significant increase in power/ground supply voltage variation and resultant VLSI performance variation, which needs to be taken into account in timing verification and delay test. In this paper, we present a P/G supply voltage variation-aware path delay test pattern generation method. Our experimental results on an AES cipher show that our proposed method finds a maximum of 2.76% power supply voltage drop and 2.62% resultant critical path delay increase, while random test pattern generation of 60 runs finds a maximum of 1.52% power supply voltage drop and 0.31% resultant critical path delay increase in average for two power supply network configurations.