Phase-locked loop design with SPO detection and charge pump trimming for reference spur suppression

As an important factor for long-term jitter in clock synthesis and distribution, reference spurs result from circuit mismatch and nonlinear effects that induce periodic perturbations in phase-locked loops (PLLs). In this paper, a PLL with built-in static phase offset (SPO) detector and charge pump current trimming for self-calibration circuits is proposed. By adjusting the charge pump current ratio determined by an SPO detector, minimum and maximum improvements of 12dB and 22.99dB in reference spur suppression can be achieved. The best improvement reduces the integrated jitter by 10% over a 10kHz to 10MHz bandwidth. The technique is demonstrated for a PLL output frequency from 400 MHz to 1 GHz. The ring oscillator based PLL is designed with 200 KHz bandwidth and 70 degree phase margin. Measurement results from chips across different corners are provided to verify the calibration technique.