• DocumentCode
    142094
  • Title

    An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model

  • Author

    Cheng-Hung Wu ; Kuen-Jong Lee ; Wei-Cheng Lien

  • Author_Institution
    Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • fYear
    2014
  • fDate
    13-17 April 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    This paper proposes an efficient diagnosis-aware ATPG method that can quickly identify equivalent-fault pairs and generate diagnosis patterns for nonequivalent-fault pairs, where an (non)equivalent-fault pair contains two stuck-at faults that are (not) equivalent. A novel fault injection method is developed which allows one to embed all fault pairs undistinguished by the conventional test patterns into a circuit model with only one copy of the original circuit. Each pair of faults to be processed is transformed to a stuck-at fault and all fault pairs can be dealt with by invoking an ordinary ATPG tool for stuck-at faults just once. High efficiency of diagnosis pattern generation can be achieved due to 1) the circuit to be processed is read only once, 2) the data structure for ATPG process is constructed only once, 3) multiple fault pairs can be processed at a time, and 4) only one copy of the original circuit is needed. Experimental results show that this is the first reported work that can achieve 100% diagnosis resolutions for all ISCAS´89 and IWLS´05 benchmark circuits using an ordinary ATPG tool. Furthermore, we also find that the total number of patterns required to deal with all fault pairs in our method is smaller than that of the current state-of-the-art work.
  • Keywords
    automatic test pattern generation; fault diagnosis; ISCAS´89 benchmark circuit; IWLS´05 benchmark circuit; automatic test pattern generation; diagnosis pattern generation; diagnosis-aware ATPG method; fault injection; fault pairs diagnosis; nonequivalent-fault pairs; single circuit model; stuck-at faults; Automatic test pattern generation; Central Processing Unit; Circuit faults; Fault diagnosis; Integrated circuit modeling; Logic gates; Multiplexing; Fault diagnosis; diagnosis pattern generation; multi-pair diagnosis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium (VTS), 2014 IEEE 32nd
  • Conference_Location
    Napa, CA
  • Type

    conf

  • DOI
    10.1109/VTS.2014.6818790
  • Filename
    6818790