• DocumentCode
    142106
  • Title

    Test-time optimization in NOC-based manycore SOCs using multicast routing

  • Author

    Agrawal, Meena ; Chakrabarty, Krishnendu

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
  • fYear
    2014
  • fDate
    13-17 April 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    A limitation of prior work on testing of network-on-chip (NOC)-based manycore SOCs is that cores are tested using unicast packets; this approach fails to exploit the homogeneity of cores in large manycore SOCs. By leveraging the capability of modern multicast routers to fork a flit to multiple destination ports simultaneously, we present two methods to minimize time to test cores in a homogeneous SOC with many identical cores. First, we formulate the test-time minimization problem in terms of integer linear programming. Next, we add a practical constraint, model the constrained problem in terms of grid partitioning, and apply dynamic programming (DP) to optimally solve it. We present results on synthetic NOC-based SOCs constructed using cores from the ITC´02 benchmarks to show that the proposed methods significantly outperform prior methods based on unicast, and demonstrate the scalability of the DP-based approach for an SOC consisting of more than 1,000 cores.
  • Keywords
    integer programming; integrated circuit design; integrated circuit testing; linear programming; network-on-chip; ITC´02 benchmarks; NOC; SOC; dynamic programming; grid partitioning; integer linear programming; multicast routing; network-on-chip testing; test-time minimization; test-time optimization; unicast packets; Dynamic programming; Multicast communication; Particle separators; Pins; Routing; System-on-chip; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium (VTS), 2014 IEEE 32nd
  • Conference_Location
    Napa, CA
  • Type

    conf

  • DOI
    10.1109/VTS.2014.6818797
  • Filename
    6818797