Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS

Author

Pawlowski, Robert ; Crop, Joseph ; Cho, Moonju ; Tschanz, James ; De, Vivek ; Fairbanks, Tom ; Quinn, Heather ; Borkar, Shekhar ; Chiang, Patrick Yin

Author_Institution

Sch. of EECS, Oregon State Univ., Corvallis, OR, USA

fYear

2014

fDate

15-17 Sept. 2014

Firstpage

1

Lastpage

4

Abstract

This work details a process-portable test chip, fabricated in 65nm CMOS, specifically designed to measure radiation-induced soft error rate (SER) during operation at near-threshold. A variety of SRAM, register file (RF), and digital logic test structures are included that provide a comprehensive assessment of circuit sensitivities to radiation at low V_DD. Neutron irradiation measurements of SRAM/RF show a 6.45x increase in SER when V_DD is lowered from 1.0V to 0.33V, and a 2.6x increase in multi-bit upsets. Alpha bombardment of digital logic tests demonstrates the effectiveness of this test chip platform in characterizing the relationship between SER and different circuit characteristics when operating at low V_DD.

Keywords

CMOS memory circuits; SRAM chips; integrated circuit testing; logic testing; neutron effects; radiation hardening (electronics); CMOS integrated circuit; digital logic tests; logic soft errors; neutron irradiation measurements; process portable test chip; radiation induced SRAM; radiation induced soft error rate; size 65 nm; voltage 0.33 V to 1.0 V; CMOS integrated circuits; Error analysis; Integrated circuit modeling; Inverters; Market research; Neutrons; Random access memory; logic; memory; near-threshold; reliability; soft errors;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2014.6946138

Filename

6946138