Title :
65 nm CMOS receiver with 4.2 dB NF and 66 dB gain for 60 GHz applications
Author :
Wang, N.Y. ; Wu, Huwei ; Liu, J.Y.C. ; Chang, Mau-Chung Frank
Author_Institution :
Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA
Abstract :
A direct conversion receiver for 60 GHz applications is fabricated in 65 nm CMOS. It consists of three low-noise amplifier gain stages, an RF mixer, a lowpass filter and a three-stage programmable gain amplifier. An overall minimum noise figure (NF) of 4.2 dB and maximum gain of 66 dB is achieved by the receiver occupying a core area of 0.26 mm2 while drawing 36 mA of current from a 1 V supply.
Keywords :
CMOS integrated circuits; MMIC; radio receivers; RF mixer; bw-noise amplifier gain stages; current 36 mA; frequency 60 GHz; gain 66 dB; lowpass filter; noise figure 4.2 dB; size 65 nm; three-stage programmable gain amplifier; voltage 1 V;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2010.3094
