DocumentCode :
1421483
Title :
Low-power 4-bit flash analogue to digital converter for ranging applications
Author :
Torfs, G. ; Li, Zuyi ; Bauwelinck, J. ; Yin, X. ; Van der Plas, G. ; Vandewege, J.
Author_Institution :
INTEC/IMEC, Ghent Univ., Ghent, Belgium
Volume :
47
Issue :
1
fYear :
2011
Firstpage :
20
Lastpage :
22
Abstract :
A 4-bit 700 MS/s flash ADC is presented in 0.18 m CMOS. By lowering the kickback noise of the individual comparators it was possible to reduce the power consumption to 4.43 mW. Improved calibration capabilities resulted in an INL and DNL smaller than 0.25 LSB. These low nonlinearities give rise to 3.77 effective number of bits at the Nyquist input frequency and this in turn yields an overall figure of merit of 0.46 pJ per conversion step, the lowest figure of merit reported for ADCs with sampling rate above 500 MHz in 0.18 m CMOS.
Keywords :
CMOS integrated circuits; analogue-digital conversion; low-power electronics; CMOS; flash ADC; low-power 4-bit flash analogue to digital converter;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el.2010.2213
Filename :
5682179
Link To Document :
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