Title :
Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time
Author :
Ding, Yiqiang ; Zhang, Wei
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ. Carbondale, Carbondale, IL, USA
fDate :
6/1/2010 12:00:00 AM
Abstract :
Estimating and optimizing worst-case execution time (WCET) is critical for hard real-time systems to ensure that different tasks can meet their respective deadlines. Recent work has shown that simple prefetching techniques such as the Next-N-Line prefetching can enhance both the average-case and worst-case performance; however, the improvement on the worst-case execution time is rather limited and inefficient. This paper studies a loop-based instruction prefetching approach, which can exploit the program control-flow information to intelligently prefetch instructions that are most likely needed. Our evaluation indicates that the loop-based instruction prefetching outperforms the Next-N-Line prefetching in both the worst-case and the average-case performance for real-time applications.
Keywords :
cache storage; program control structures; real-time systems; Next-N-Line prefetching; cache memories; hard real-time systems; loop-based instruction prefetching; program control-flow information; worst-case execution time reduction; Automobiles; Cache memory; Embedded system; Information analysis; Microprocessors; Pollution; Prefetching; Real time systems; Time measurement; Timing; Real-time and embedded systems; cache memories.;
Journal_Title :
Computers, IEEE Transactions on