• DocumentCode
    1421547
  • Title

    Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time

  • Author

    Ding, Yiqiang ; Zhang, Wei

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Southern Illinois Univ. Carbondale, Carbondale, IL, USA
  • Volume
    59
  • Issue
    6
  • fYear
    2010
  • fDate
    6/1/2010 12:00:00 AM
  • Firstpage
    855
  • Lastpage
    864
  • Abstract
    Estimating and optimizing worst-case execution time (WCET) is critical for hard real-time systems to ensure that different tasks can meet their respective deadlines. Recent work has shown that simple prefetching techniques such as the Next-N-Line prefetching can enhance both the average-case and worst-case performance; however, the improvement on the worst-case execution time is rather limited and inefficient. This paper studies a loop-based instruction prefetching approach, which can exploit the program control-flow information to intelligently prefetch instructions that are most likely needed. Our evaluation indicates that the loop-based instruction prefetching outperforms the Next-N-Line prefetching in both the worst-case and the average-case performance for real-time applications.
  • Keywords
    cache storage; program control structures; real-time systems; Next-N-Line prefetching; cache memories; hard real-time systems; loop-based instruction prefetching; program control-flow information; worst-case execution time reduction; Automobiles; Cache memory; Embedded system; Information analysis; Microprocessors; Pollution; Prefetching; Real time systems; Time measurement; Timing; Real-time and embedded systems; cache memories.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2010.44
  • Filename
    5416687