DocumentCode
1421588
Title
FPGA Designs with Optimized Logarithmic Arithmetic
Author
Fu, Haohuan ; Mencer, Oskar ; Luk, Wayne
Author_Institution
Dept. of Geophys., Stanford Univ., Stanford, CA, USA
Volume
59
Issue
7
fYear
2010
fDate
7/1/2010 12:00:00 AM
Firstpage
1000
Lastpage
1006
Abstract
Using a general polynomial approximation approach, we present an arithmetic library generator for the logarithmic number system (LNS). The generator produces optimized LNS arithmetic libraries that improve significantly over previous LNS designs on area and latency. We also provide area cost estimation and bit-accurate simulation tools that facilitate comparison between LNS and floating-point designs.
Keywords
field programmable gate arrays; floating point arithmetic; logic design; polynomial approximation; FPGA designs; arithmetic library generator; floating point designs; general polynomial approximation approach; logarithmic number system; optimized logarithmic arithmetic; Arithmetic; Costs; Delay; Design optimization; Educational institutions; Field programmable gate arrays; Geophysics computing; Hardware; Libraries; Polynomials; Table lookup; Throughput; Reconfigurable hardware; computer arithmetic; computer systems organization; general; mathematics of computing.; numerical analysis; special-purpose and application-based systems;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.2010.51
Filename
5416693
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