• DocumentCode
    1422615
  • Title

    Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications

  • Author

    Joshi, Rimesh M. ; Madanayake, Arjuna ; Adikari, Jithra ; Bruton, Len T.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Akron, Akron, OH, USA
  • Volume
    20
  • Issue
    12
  • fYear
    2012
  • Firstpage
    2241
  • Lastpage
    2254
  • Abstract
    A broadband digital beamforming algorithm is proposed for directional filtering of temporally-broadband bandpass space-time plane-waves at radio frequencies (RFs). The enhancement of desired waves, as well as rejection of undesired interfering plane-waves, is simulated. A systolic- and wavefront-array architecture is proposed for the real-time implementation of second-order spatially-bandpass (SBP) 2-D infinite impulse response (IIR) beam filters having potential applications in broadband beamforming of temporally down-converted RF signals. The higher speed of operation and potentially reduced power consumption of the asynchronous architecture of wavefront-array processors (WAPs) in comparison to the conventional synchronous hardware has emerging applications in radio-astronomy, radar, navigation, space science, cognitive radio, and wireless communications. Further, the bit error rate (BER) performance improvement along with the reduced computational complexity of the 2-D IIR SBP frequency-planar digital filter over digital phased array feed (PAF) beamformer is provided. A nominal BER versus signal-to-interference ratio (SIR) gain of 10-16 dB compared to case where beamforming is not applied, and a gain of 2-3 dB at approximately half the number of parallel multipliers to digital PAF, are observed. The results of application-specific integrated circuit (ASIC) synthesis of the digital filter designs are also presented.
  • Keywords
    IIR filters; application specific integrated circuits; array signal processing; radiocommunication; 2D IIR beam filter; ASIC; application specific integrated circuit; array processor realization; array processor synthesis; bit error rate performance; broadband digital beamforming algorithm; computational complexity; digital filter design; digital phased array feed beamformer; directional filtering; interfering plane wave; radio frequencies; signal-to-interference ratio; spatially bandpass 2D infinite impulse response beam filters; synchronous hardware; systolic array architecture; temporally broadband bandpass space-time plane wave; wavefront array architecture; wavefront array processor; wireless applications; wireless communication; Array signal processing; Bit error rate; Broadband communication; Digital filters; Field programmable gate arrays; IIR filters; Array processors; bit error rate (BER); digital phased array feed (PAF); field-programmable gate array (FPGA); multidimensional digital filters; spatial modulation; systolic; wavefront; wireless;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2011.2174167
  • Filename
    6130581