Early voltages associated with temperature effects on strained MOSFET devices

Nano-process MOSFET devices are considered to be upgraded by strained engineering technique. Mismatched lattice constants between SiGe and silicon is used to form global strain over the whole devices, while silicon nitride as contact etching stop layer (CESL) is applied to the top of the devices to squeeze the devices uni-axially. Both are found to be capable of enhancing the electrical properties compared to the ones of devices without either. The 1.5 nm silicon cap is introduced for the benefit of forming gate oxide. I_D-V_D characteristics curves are apparently improved as the strained engineering technique is taken into account. The variations of Early voltages at different temperatures are determined and found to vanish at certain gate bias, denoted by V_G. This regularity of Early Voltage can be addressed by modeled lambda parameters which is V_G dependent and thus associated with the depletion region width underneath the gate oxide.