Title :
New hardware architecture for fast raster image generation
Author :
Kim, S.S. ; Kyung, C.M.
Author_Institution :
Dept. of Electr. Eng., Kaist, Seoul
fDate :
3/31/1988 12:00:00 AM
Abstract :
Describes a new hardware architecture known as an edge painting tree (EPT) pipelined binary trees for fast generation of scanline images for raster scan graphics targeted for surface or solid modelling. The hardware complexity of EPT is much smaller than that of earlier raster graphics engines owing to the use of 1 bit logic rather than log2 P bit logic where P is the number of pixels per scanline
Keywords :
computer architecture; computer graphic equipment; computerised picture processing; 1 bit logic; EPT; edge painting tree; fast generation of scanline images; fast raster image generation; hardware architecture; hardware complexity; image processing; increased speed; pipelined binary trees; raster scan display; raster scan graphics; reduced hardware complexity; solid modelling; surface modelling;
Journal_Title :
Electronics Letters
