Gate etch induced diode leakage prevention with 7-nm CVD stacked gate dielectric

Using a CVD stacked oxide, containing a thermally grown layer and a deposited CVD film, as the gate dielectric for MOS devices provides significant advantages over a single thermally grown oxide, due to mismatch of weak spots in the two layers, reduced substrate consumption and stress compensation between component layers. This paper discusses how a 7-nm stacked gate oxide reduced process-induced diode leakage by /spl sim/10/sup 2/, an advantage not reported previously. Micropore misalignment in the two component layers of the stacked gate oxide preventing the reactive etchant ions from reaching the substrate could explain the enhanced "etch stop" provided by the stacked oxide.