Title :
Robust asymmetric 6T-SRAM cell for low-power operation in nano-CMOS technologies
Author :
Azam, T. ; Cheng, Binjie ; Roy, Sandip ; Cumming, David R. S.
Author_Institution :
Dept. of Electron. & Electr. Eng., Univ. of Glasgow, Glasgow, UK
Abstract :
An asymmetric 6T-SRAM cell design is presented for reliable low-power circuit operation under large variability. A low overhead write assist circuit is added to increase the write-noise-margin (WNM) and improve the write speed/power. Sizing is used to strengthen the pull-down transistor of the feedback inverter of the single ended read circuit to enhance the static-noise-margin (SNM). Monte Carlo simulations indicate a 90% improvement in SNM and a boost in the WNM of 108% compared to the conventional 6T-SRAM design. Comparative analysis of a 65nm 64 ?? 32 bit SRAM designed using both SRAM cells (Symmetric-6T and Asymmetric-6T) shows the write delay and power decrease by 46% and 35%, respectively, while total power decreases by 52% using the proposed design.
Keywords :
CMOS memory circuits; Monte Carlo methods; SRAM chips; circuit simulation; integrated circuit design; integrated circuit noise; nanoelectronics; Monte Carlo simulations; complementary metal-oxide-semiconductor; feedback inverter; low overhead write assist circuit; low-power circuit operation; nanoCMOS technology; pull-down transistor; robust asymmetric 6T-SRAM cell design; single ended read circuit; size 65 nm; static random access memory; static-noise-margin; storage capacity 32 bit; storage capacity 64 bit; total power; write delay; write power; write speed; write-noise-margin;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2010.2817
