DocumentCode :
1423023
Title :
Mesh routing topologies for multi-FPGA systems
Author :
Hauck, Scott ; Borriello, Gaetano ; Ebeling, Carl
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
Volume :
6
Issue :
3
fYear :
1998
Firstpage :
400
Lastpage :
408
Abstract :
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and delay of the resulting system. Crossbar, Hierarchical Crossbar, and Mesh interconnection schemes have all been proposed for use in FPGA-based systems. In this paper, we examine Mesh interconnection schemes, and propose several constructs for more efficient topologies. These reduce interchip delays by more than 60% over the basic four-way Mesh.
Keywords :
field programmable gate arrays; logic design; network routing; network topology; Mesh interconnection; design; mesh routing topology; multi-FPGA system; Circuit testing; Emulation; Hardware; Integrated circuit interconnections; Logic arrays; Logic testing; Programmable logic arrays; Reconfigurable logic; Routing; Topology;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.711311
Filename :
711311
Link To Document :
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