• DocumentCode
    1423167
  • Title

    Memory efficient software synthesis with mixed coding style from dataflow graphs

  • Author

    Sung, Wonyong ; Ha, Soonhoi

  • Author_Institution
    CAP Lab., Seoul Nat. Univ., South Korea
  • Volume
    8
  • Issue
    5
  • fYear
    2000
  • Firstpage
    522
  • Lastpage
    526
  • Abstract
    This paper presents a set of techniques to reduce the code and data sizes for software synthesis from graphical digital signal-processing programs based on the synchronous dataflow model. By sharing the kernel code among multiple instances of a block with a shared function, we can further reduce the code size below the previous results based on inline coding style. A systematic approach also is devised to give up the single appearance schedule for reducing the data buffer requirement. The proposed techniques have been evaluated with two real-life examples to prove their significance.
  • Keywords
    automatic programming; data flow graphs; embedded systems; program compilers; appearance schedule; code size; data buffer requirement; data size; dataflow graphs; graphical digital signal-processing programs; inline coding style; kernel code; memory efficient software synthesis; mixed coding style; shared function; synchronous dataflow model; Computer buffers; Digital signal processing; Dynamic scheduling; Embedded system; Kernel; Memory management; Processor scheduling; Signal synthesis; Switches; System-on-a-chip;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/92.894156
  • Filename
    894156