DocumentCode
1423232
Title
Line coverage of path delay faults
Author
Majhi, Ananta K. ; Agrawak, V.D. ; Jacob, James ; Patnaik, Lalit M.
Author_Institution
Indian Inst. of Sci., Bangalore, India
Volume
8
Issue
5
fYear
2000
Firstpage
610
Lastpage
614
Abstract
We propose a new coverage metric for delay fault tests. The coverage is measured for each line with a rising and a falling transition, but the test criterion differs from that of the slow-to-rise and slow-to-fall transition faults. A line is tested by a line delay test, which is a robust path delay test for the longest sensitizable path producing a given transition on the target line. Thus, the test criterion resembles path delay test and not the gate or transition delay test. Yet, the maximum number of tests (or faults) is limited to twice the number of lines. In a two-pass test-generation procedure, we first attempt delay tests for a minimal set of longest paths for all lines. Fault simulation is used to determine the coverage metric. For uncovered lines, in the second pass, several paths of decreasing lengths are targeted. We give results for several benchmark circuits.
Keywords
VLSI; automatic test pattern generation; delays; digital integrated circuits; fault simulation; integrated circuit testing; logic testing; ATPG; VLSI testing; coverage metric; fault simulation; line coverage; line delay test; path delay faults; robust path delay test; test criterion; two-pass test-generation procedure; Circuit faults; Circuit simulation; Circuit testing; Delay effects; Delay lines; Jacobian matrices; Logic testing; Robustness; System testing; Very large scale integration;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/92.894166
Filename
894166
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