DocumentCode
1423477
Title
Design techniques for testable embedded error checkers
Author
McCluskey, E.J.
Author_Institution
Comput. Syst. Lab., Stanford Univ., CA, USA
Volume
23
Issue
7
fYear
1990
fDate
7/1/1990 12:00:00 AM
Firstpage
84
Lastpage
88
Abstract
Design techniques to ensure the testability of embedded checkers that cannot be tested by scan-path bistables are presented. The discussion covers: types of error detectors; parity checkers and self-testing circuits; two-rail checkers; M-out-of-N checkers; and equality checkers. The techniques outline guarantee single stuck fault testability.<>
Keywords
error correction; error detection; fault tolerant computing; M-out-of-N checkers; design techniques; equality checkers; parity checkers; self-testing circuits; single stuck fault testability; testable embedded error checkers; two-rail checkers; types of error detectors; Circuit faults; Circuit testing; Computer errors; Detectors; Digital systems; Error correction codes; Fault detection; Signal design; Signal detection; System testing;
fLanguage
English
Journal_Title
Computer
Publisher
ieee
ISSN
0018-9162
Type
jour
DOI
10.1109/2.56855
Filename
56855
Link To Document