DocumentCode
1423481
Title
Improved output ESD protection by dynamic gate floating design
Author
Chang, Hun-Hsien ; Ker, Ming-Dou
Author_Institution
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
45
Issue
9
fYear
1998
fDate
9/1/1998 12:00:00 AM
Firstpage
2076
Lastpage
2078
Abstract
A dynamic gate floating design is proposed to improve ESD robustness of the CMOS output buffers with small drive capability. By using this novel design, the human-body-model (machine-model) ESD failure threshold of a 2-mA CMOS output buffer has been practically improved from 1 KV (100 V) to greater than 8 KV (1500 V) in a 0.35-μm CMOS process
Keywords
CMOS integrated circuits; buffer circuits; electrostatic discharge; protection; 0.35 micron; 2 mA; 8 kV; CMOS output buffer; ESD protection; dynamic gate floating design; failure threshold; human body model; machine model; CMOS process; CMOS technology; Electrostatic discharge; Fingers; Libraries; MOS devices; Protection; Robustness; Transistors; Variable structure systems;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.711378
Filename
711378
Link To Document