Title :
Efficient back-bias voltage generator with suppressed parasitic bipolar action for low voltage DRAMs
Author_Institution :
Advanced DRAM Design Dept., Hyundai Electron. Ind. Co. Ltd., Cheongju, South Korea
fDate :
1/4/2001 12:00:00 AM
Abstract :
A high-efficiency back-bias voltage generator with a cross-coupled hybrid pumping circuit (CHPC2) is presented. This scheme suppresses the parasitic bipolar turning-on so as not to lose the pumping current into the parasitic n-p-n bipolar transistor. The proposed generator exhibits better efficiency and faster pumping speed compared with previous bipolar-suppressed back-bias voltage generators
Keywords :
CMOS memory circuits; DRAM chips; low-power electronics; LV dynamic RAM; back-bias voltage generator; cross-coupled hybrid pumping circuit; high-efficiency voltage generator; low voltage DRAMs; parasitic bipolar action suppression; parasitic n-p-n bipolar transistor;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010047
