Title :
Functionally testable path delay faults on a microprocessor
Author :
Lai, Wei-Cheng ; Krstic, Angela ; Cheng, Kwang-Ting
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
The impact of delay defects on these functionally untestable paths on overall circuit performance involves identification of such paths determining the achievable path delay fault coverage and reducing the subsequent test generation effort. The experimental results for two microprocessors (Parwan and DLX) indicate that a significant percentage of structurally testable paths are functionally untestable
Keywords :
logic testing; microprocessor chips; circuit performance; delay defects; microprocessor; microprocessors; path delay fault coverage; structurally testable paths; test generation; testable path delay faults; Circuit faults; Circuit optimization; Circuit testing; Delay effects; Fault diagnosis; Flip-flops; Microprocessors; Propagation delay; Registers; Signal processing;
Journal_Title :
Design & Test of Computers, IEEE
