Optimization of the optical sensitivity of p-i-n FET receivers

The optimization of the input stage of a p-i-n FET receiver is discussed, with emphasis on the implications for an integrated InP/InGaAs p-i-n FET technology. In the early stages of development of this technology, it is necessary to keep the design simple, which implies that the device will consist of a single-stage, low-gain amplifier. Design criteria for such an amplifier are presented, and it is shown that the transimpedance configuration provides better sensitivity than a voltage amplifier, even when the gain of the amplifier is very small. It is also shown that the gate capacitance (i.e. width) of the input FET which optimizes the sensitivity is much smaller when the amplifier gain is low than it is in the high-gain limit.<>