• DocumentCode
    1424753
  • Title

    Multipattern Scan-Based Test Sets With Small Numbers of Primary Input Sequences

  • Author

    Pomeranz, Irith

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • Volume
    31
  • Issue
    2
  • fYear
    2012
  • Firstpage
    322
  • Lastpage
    326
  • Abstract
    When a multipattern scan-based test is applied at-speed to detect delay defects, it is necessary to change the primary input vectors at-speed. However, tester limitations can make this infeasible. The solution where the primary input vectors are held constant during the test reduces the fault coverage. An alternative solution is to store the primary input sequences of a multipattern test set on-chip and apply them at-speed from an on-chip memory. To support such a solution, this paper describes a procedure for computing a multipattern test set that requires a small number of different primary input sequences. Experimental results for single stuck-at faults and for transition faults show that a multipattern test set that detects all the detectable faults requires a number of primary input sequences that is significantly smaller than the number of tests.
  • Keywords
    fault diagnosis; integrated circuit reliability; integrated circuit testing; sequences; storage management chips; delay defect detection; fault coverage; multipattern scan-based test sets; multipattern test set on-chip; on-chip memory; primary input sequences; single stuck-at faults; transition faults; Circuit faults; Clocks; Computational modeling; Delay; Runtime; System-on-a-chip; Vectors; At-speed testing; full-scan circuits; multipattern tests; single stuck-at faults; transition faults;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2011.2170070
  • Filename
    6132654