Title :
VLSI implementation of visual block pattern truncation coding
Author :
Liu, Yuan-Chen ; Lai, Yeong-Kang ; Tsai, Tsung-Han ; Wu, Po-Cheng ; Chen, Liang-Gee
Author_Institution :
Dept. of Comput. & Inf. Sci., Tamsui Oxford Univ. Coll., Taipei, Taiwan
fDate :
8/1/1998 12:00:00 AM
Abstract :
The paper proposes a pipelined architecture of a visual block pattern truncation coding algorithm to minimize the mean square error. Using this chip, the VBPTC based system can be applied to real-time encoding for moving pictures
Keywords :
CMOS digital integrated circuits; VLSI; correlation methods; digital signal processing chips; image coding; pipeline processing; 0.6 micron; SPTM CMOS process; VLSI implementation; block correlated signals; image coding; mean square error; moving pictures; pipelined architecture; real-time encoding; visual block pattern truncation coding; visual block pattern truncation coding algorithm; Bit rate; Educational institutions; Geometry; Image coding; Information science; Mean square error methods; Pixel; Redundancy; Very large scale integration; Videoconference;
Journal_Title :
Consumer Electronics, IEEE Transactions on
