Title :
A single-chip HDTV video decoder design
Author :
Meyer, Roland ; Phillips, Linsey
fDate :
8/1/1998 12:00:00 AM
Abstract :
The development has been compared for a single-chip MPEG2 main profile @ high-level video decoder that decodes and displays all 18 ATSC digital video formats, including HDTV. Additionally, it can ”downconvert“ HDTV inputs to SDTV resolution and incorporates programmable filters for display output reformatting. By using Rambus DRAM technology, adequate memory performance was achieved for a single-chip implementation. Applications include digital TV receivers, set-top boxes and computers
Keywords :
DRAM chips; decoding; digital signal processing chips; digital television; high definition television; image resolution; programmable filters; television receivers; video coding; ATSC digital video formats; MPEG2 main profile @ high-level; Rambus DRAM technology; SDTV resolution; digital TV receivers; display output reformatting; down conversion system; memory performance; programmable filters; set-top boxes; single-chip HDTV video decoder design; Auditory displays; Computer displays; Costs; Decoding; Digital TV; Filters; HDTV; Random access memory; TV receivers; US Department of Transportation;
Journal_Title :
Consumer Electronics, IEEE Transactions on
