DocumentCode :
1424913
Title :
Functional Test Generation Using Efficient Property Clustering and Learning Techniques
Author :
Chen, Mingsong ; Mishra, Prabhat
Author_Institution :
Dept. of Comput. & Inf. Sci. & Eng., Univ. of Florida, Gainesville, FL, USA
Volume :
29
Issue :
3
fYear :
2010
fDate :
3/1/2010 12:00:00 AM
Firstpage :
396
Lastpage :
404
Abstract :
Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for generating efficient tests. Several promising ideas using bounded model checking are proposed over the years to efficiently generate counterexamples (tests). The existing researchers have used incremental satisfiability to improve the counterexample generation, involving only one property by sharing knowledge across instances of the same property with incremental bounds. In this paper, we present a framework that can efficiently reduce the overall test generation time by exploiting the similarity among different properties. This paper makes two primary contributions: (1) it proposes novel methods to cluster similar properties; and (2) it develops efficient learning techniques that can significantly reduce the overall test generation time for the properties in a cluster by sharing knowledge across similar test generation instances. Our experimental results using both software and hardware benchmarks demonstrate that our approach can drastically reduce (on average three to five times) the overall test generation time compared to existing methods.
Keywords :
circuit CAD; computability; formal verification; integrated circuit design; integrated circuit testing; learning (artificial intelligence); pattern clustering; system-on-chip; bounded model checking; functional test generation; functional verification; incremental satisfiability; knowledge sharing; pattern clustering; system-on-chip design; Automatic testing; Benchmark testing; Career development; Hardware; Humans; Performance evaluation; Software testing; System testing; System-on-a-chip; Time to market; Bounded model checking; SAT; functional verification; property clustering; test generation;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2010.2041846
Filename :
5419232
Link To Document :
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