Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Abstract :
In this paper, we present DeFer-a fast, high-quality, scalable, and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a nonslicing floorplan by compacting a slicing floorplan. To find a good slicing floorplan, instead of searching through numerous slicing trees by simulated annealing as in traditional approaches, DeFer considers only one single slicing tree. However, we generalize the notion of slicing tree based on the principle of deferred decision making (DDM). When two subfloorplans are combined at each node of the generalized slicing tree, DeFer does not specify their orientations, the left-right/top-bottom order between them, and the slice line direction. DeFer even does not specify the slicing tree structure for small subfloorplan. In other words, we are deferring the decisions on these factors, which are specified arbitrarily at an early step in traditional approaches. Because of DDM, one slicing tree actually corresponds to a large number of slicing floorplan solutions, all of which are efficiently maintained in one single shape curve. With the final shape curve, it is straightforward to choose a good floorplan fitting into the fixed outline. Several techniques are also proposed to further optimize the wirelength. For both fixed-outline and classical floorplanning problems, experimental results show that DeFer achieves the best success rate, the best wirelength, the best runtime, and the best area on average compared with all other state-of-the-art floorplanners.
Keywords :
VLSI; circuit layout; decision making; integrated circuit design; simulated annealing; DeFer; deferred decision making; fixed-outline floorplanning algorithm; simulated annealing; single shape curve; slicing trees; state-of-the-art; Circuit simulation; Computational modeling; Decision making; Distributed decision making; Integrated circuit interconnections; Runtime; Shape; Simulated annealing; Tree data structures; Very large scale integration; Deferred decision making; fixed outline; floorplanning; layout optimization;