Title :
An ASIC implementation of an optimized digital video encoder
Author :
Oh, Seung Ho ; Han, Sun-Hyoung ; Kang, Bongsoon ; Lee, Moon Key
Author_Institution :
Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea
fDate :
8/1/1998 12:00:00 AM
Abstract :
This paper presents a design of an optimized video encoder using a simple pipelined architecture. The proposed video encoder accepts conventional NTSC/PAL video signals. It also processes the PALplus video signal using an improved decimation process. The proposed encoder requires only 25 K gates, which is a 41% reduction in hardware compared with the systolic pipelined architecture of Oh, Choi, Kwon and Lee (see ibid., vol.43, no.3, p.965-71, 1997). The encoder has been designed in a 5-stage pipelined structure to assure stable operation. The overall performance of the encoder has been verified by using 0.65 μm CMOS gate array technology. The chip size is 5170 μm * 435O μm
Keywords :
CMOS logic circuits; application specific integrated circuits; circuit optimisation; circuit stability; digital signal processing chips; logic arrays; low-pass filters; pipeline processing; video coding; 0.65 micron; ASIC implementation; CMOS gate array technology; NTSC/PAL video signals; chip size; decimation process; gates; hardware reduction; low pass filter; optimized digital video encoder; performance; pipelined architecture; stable operation; video signal processing; Application specific integrated circuits; CMOS technology; Design automation; Design optimization; Electronic mail; Frequency; Hardware; Large scale integration; Signal processing; TV broadcasting;
Journal_Title :
Consumer Electronics, IEEE Transactions on
