Title :
A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator
Author :
Chuang, Pierce ; Li, David ; Sachdev, Manoj
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada
Abstract :
A single-cycle 64-bit binary comparator utilizing a radix-2 tree structure is proposed in this brief. This novel comparator architecture is specifically designed for static logic to achieve both low-power and high-performance operation, particularly at low-input data activity environments. This brief presents a detailed performance and power analysis of various state-of-the-art comparator designs across three CMOS technologies. At 65-nm technology, with 25% (10%) data activity, the proposed design demonstrates 2.3 × (3.5 x) and 3.7 × (5.8 x) power and energy-delay product efficiency, respectively. In addition, the proposed work is 2.7 × faster at iso-energy(80 fJ) or 3.3 × more energy efficient at iso-delay(200 ps) than existing designs.
Keywords :
CMOS logic circuits; comparators (circuits); digital arithmetic; logic design; low-power electronics; trees (mathematics); CMOS technology; comparator architecture; high-performance operation; iso-delay; iso-energy; low-input data activity environments; low-power high-performance single-cycle tree-based binary comparator; low-power operation; power analysis; product efficiency; radix-2 tree structure; single-cycle binary comparator; state-of-the-art comparator design; static logic; word length 64 bit; Algorithm design and analysis; CMOS integrated circuits; Clocks; Delay; Logic gates; Power demand; Transistors; Binary comparator; digital arithmetic;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2011.2180110
