Title :
Behavior Analysis of an LDD Poly-Si TFT Using 2-D Device Simulation
Author_Institution :
Dept. of Electron. & Inf., Ryukoku Univ., Otsu, Japan
fDate :
3/1/2012 12:00:00 AM
Abstract :
We have analyzed the device behavior of a poly-Si thin-film transistor (TFT) with a lightly doped drain (LDD) structure using 2-D device simulation. It is found that the reason that the on current does not fall very much is that the electron channel oozes from the channel region to the LDD region and the electric current paths spread to the entire LDD region. On the other hand, the reason that the off current is effectively reduced is undoubtedly that the electric field at the interface between the channel and LDD regions is weakened. However, it should be noted that the depletion region is formed at the drain edge owing to the “pseudo” space-charge region in the channel region, where the carrier density is much lower than in the other channel region, although the net space-charge does not exist.
Keywords :
electric fields; elemental semiconductors; silicon; space charge; thin film transistors; 2D device simulation; LDD polySi TFT; Si; behavior analysis; depletion region; drain edge formation; electric field current path; electron channel region; lightly doped drain polySi thin-film transistor; off current; on current; pseudospace-charge region; Analytical models; Awards activities; Charge carrier density; Educational institutions; Logic gates; Thin film transistors; Lightly doped drain (LDD); poly-Si; pseudo space-charge region; thin-film transistor (TFT); two-dimensional (2-D) device simulation;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2011.2180531