DocumentCode
1426439
Title
OBDD minimization based on two-level representation of Boolean functions
Author
Yu-Liang Wu ; Hongbing Fan ; Marek-Sadowska, M. ; Wong, C.K.
Author_Institution
Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong
Volume
49
Issue
12
fYear
2000
Firstpage
1371
Lastpage
1379
Abstract
In this paper, we analyze the basic properties of some Boolean function classes and propose a low complexity OBDD variable ordering algorithm, which is exact (optimum) to some classes of functions and very effective to general two-level form functions. We show that the class of series-parallel functions, which can be expressed by a factored form where each variable appears exactly once, can yield exact OBDD variable orderings in polynomial time. We also study the thin Boolean functions whose corresponding OBDDs can be represented by the form of thin OBDDs in which the number of nonterminal nodes is equal to the number of input variables. We show,that a thin Boolean function always has an essential prime cube cover and the class of series-parallel functions is a proper subset of thin Boolean functions. We propose a heuristic viewing OBDDs as evaluation machines with function cube covers as their inputs and apply a queuing principle in the algorithm design. Our heuristic, the augmented Dynamic Shortest Cube First algorithm, is proven to be optimum for the series-parallel functions and also be very effective for general two-level form functions. Experimental results on a large number of two-level form benchmark circuits show that the algorithm yields an OBDD total size reduction of over 51 percent with only 7 percent CPU time compared to the well-known network-based Fan-in Heuristic implemented in the SIS package. Comparing to the known exact results, ours is only 49 percent larger in size while only uses 0.001 percent CPU time.
Keywords
Boolean functions; binary decision diagrams; minimisation of switching nets; Boolean function classes; Boolean functions; OBDD minimization; evaluation machine; low complexity; series-parallel functions; thin Boolean functions; two-level representation; Algorithm design and analysis; Boolean functions; Central Processing Unit; Combinational circuits; Data structures; Formal verification; Input variables; Logic design; Minimization; Polynomials;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.895868
Filename
895868
Link To Document