DocumentCode
1426945
Title
Experimental investigation of voltage sag mitigation by an advanced static VAr compensator
Author
Wang, P. ; Jenkins, N. ; Bollen, M.H.J.
Author_Institution
Centre for Electr. Energy, Univ. of Manchester Inst. of Sci. & Technol., UK
Volume
13
Issue
4
fYear
1998
fDate
10/1/1998 12:00:00 AM
Firstpage
1461
Lastpage
1467
Abstract
A laboratory model of an advanced static VAr compensator (ASVC) was constructed to examine its capability for voltage sag mitigation. In this paper, the main structure of the laboratory ASVC is described briefly. Its mitigation effect on voltage sags of different magnitude is then demonstrated. The influences of its initial operation point, system impedance, and DC capacitance are considered. The behaviour of this laboratory ASVC during a phase-angle jump associated with a voltage sag is examined
Keywords
capacitance; electric impedance; invertors; power systems; static VAr compensators; DC capacitance; IGBT inverter; advanced static VAr compensator; initial operation point; phase-angle jump; system impedance; voltage sag mitigation; Costs; Hardware; Impedance; Insulated gate bipolar transistors; Laboratories; Power generation; Power quality; Reactive power; Static VAr compensators; Voltage fluctuations;
fLanguage
English
Journal_Title
Power Delivery, IEEE Transactions on
Publisher
ieee
ISSN
0885-8977
Type
jour
DOI
10.1109/61.714772
Filename
714772
Link To Document