Performance comparison between static and dynamic CMOS logic implementations of a pipelined square-rooting circuit

Pipelined cellular array implementations of arithmetic circuits are usually adopted to obtain high throughput at reasonable cost. The circuit design style used to implement the array greatly influences both performance and cost. The designer has to move in a varied and complex scenario, since nowadays scores of logic styles are known among CMOS families. Static logic styles are easy to use and they allow low power consumption, while dynamic logic styles have some potential advantages. These circuits tend to be faster and, at least for the implementation of simple logic functions, they require fewer transistors. Often the choice of the circuit design style is done by means of qualitative analysis. Referring to the creation of a pipelined square-rooting circuit, both static and dynamic implementations are quantitatively compared for several operand wordlengths. Using 0.5 μm technology parameters, a pre-layout comparison is performed in terms of net transistor area, number of transistors, propagation delay and average power dissipation. Results indicate that DOMINO logic implementation shows the best area-time-power trade-off. Then a set of standard cells has been designed to layout the DOMINO logic array. Post-layout data shows that a 32-bit array designed in this way and realised using 0.5 μm 3.3 V CMOS process reaches a maximum throughput rate up to 175 MHz, requires a silicon area of 1.4×1.4 mm² and dissipates 1.59 mW/MHz. The proposed RCA-based circuit reaches a throughput comparable to that of CLA-based square-rooting arrays, implemented using conventional static CMOS circuitry, thereby saving area and power