High performance double edge-triggered flip-flop using a merged feedback technique

Double edge-triggered flip-flops (DETFFs) use both edges of the clock to latch data and hence can lead to significant power saving over single edge-triggered flip-flops for a fixed data rate. However, existing DETFF implementations suffer from the problems of charge sharing, charge coupling, incomplete voltage swing, poor voltage scaling properties and excessive power dissipation. A new DETFF is proposed, which does not suffer from any of these problems and can operate at a clock speed which is 1.33 times that of the best double edge-triggered flip-flop available today. With reduced supply voltages, this flip-flop results in lower power dissipation and maintains a comparable performance to, if not better than, existing DETFFs