Title :
2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell
Author :
Hirano, Hiroshige ; Honda, Toshiyuki ; Moriwaki, Nobuyuki ; Nakakuma, Tetsuji ; Inoue, Atsuo ; Nakane, George ; Chaya, Shigeo ; Sumi, Tatsumi
Author_Institution :
Res. Lab., Matsushita Electron. Corp., Kyoto, Japan
fDate :
5/1/1997 12:00:00 AM
Abstract :
Nonvolatile memory embedded in microcontrollers has required a 100 ns access time at 2.0 V for mobile information terminals operating with a rechargeable battery. To achieve this, this paper proposes a new ferroelectric nonvolatile memory (FeRAM) architecture that utilizes a bitline-driven read scheme and a nonrelaxation reference cell for high-speed and low-voltage operations, respectively. Using this architecture, FeRAM with a one transistor and one capacitor per bit (1T/1C) cell can achieve 100 ns access time at 2.0 V
Keywords :
cellular arrays; ferroelectric storage; integrated memory circuits; memory architecture; random-access storage; 100 ns; 2 V; FeRAM; access time; bitline-driven read scheme; high-speed operation; low-voltage operation; memory architecture; mobile information terminals; nonrelaxation reference cell; nonvolatile ferroelectric memory; one transistor/one capacitor per bit cell; rechargeable battery; Batteries; Capacitors; EPROM; Ferroelectric films; Ferroelectric materials; Memory architecture; Microcontrollers; Nonvolatile memory; Random access memory; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
