Title :
A compact on-chip ECC for low cost flash memories
Author :
Tanzawa, Toru ; Tanaka, Tomoharu ; Takeuchi, Ken ; Shirota, Riichiro ; Aritome, Seiichi ; Watanabe, Hiroshi ; Hemink, Gertjan ; Shimizu, Kazuhiro ; Sato, Shinji ; Takeuchi, Yuji ; Ohuchi, Kazunori
Author_Institution :
Microelectron. Eng. Lab., Toshiba Corp., Kawasaki, Japan
fDate :
5/1/1997 12:00:00 AM
Abstract :
A compact on-chip error correcting circuit (ECC) for low cost flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND flash memory. The cumulative sector error rate has been improved from 10-4 to 10-10. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA
Keywords :
CMOS memory circuits; EPROM; NAND circuits; cellular arrays; circuit optimisation; error correction; fault diagnosis; integrated circuit reliability; 64 Mbit; NAND flash memory; cell area overhead; chip area; cumulative sector error rate; error correcting circuit; on-chip ECC; read data; reliability improvement; sense amplifiers; twin-well CMOS double-polysilicon single-metal technology; Circuits; Costs; Electrons; Error analysis; Error correction; Error correction codes; Flash memory; Logic; Nonvolatile memory; Threshold voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
