An on-chip ESD protection circuit with low trigger voltage in BiCMOS technology

Author

Wang, Albert Z H ; Tsay, Chen-Hui

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA

Volume

36

Issue

1

fYear

2001

fDate

1/1/2001 12:00:00 AM

Firstpage

40

Lastpage

45

Abstract

A novel low-trigger dual-direction on-chip electrostatic discharge (ESD) protection circuit is designed to protect integrated circuits (ICs) against ESD surges in two opposite directions. The compact ESD protection circuit features low triggering voltage (~7.5 V), short response time (0.18-0.4 ns), symmetric deep-snap-back I-V characteristics, and low on-resistance (~Ω). It passed the 14-kV human body model (HBM) ESD test and is very area efficient (~80 V/μm width). The new ESD protection design is particularly suitable for low-voltage or multiple-power-supply IC chips

Keywords

BiCMOS integrated circuits; electrostatic discharge; integrated circuit reliability; integrated circuit testing; low-power electronics; 0.18 to 0.4 ns; 14 kV; 7.5 V; BiCMOS technology; ESD surges; human body model test; low-voltage IC chips; multiple-power-supply IC chips; on-chip ESD protection circuit; response time; symmetric deep-snap-back I-V characteristics; trigger voltage; BiCMOS integrated circuits; Delay; Electrostatic discharge; Humans; Integrated circuit technology; Low voltage; Neodymium; Partial discharges; Silicon; Surge protection;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.896227

Filename

896227