1-V 9-bit pipelined switched-opamp ADC

Author

Waltari, Mikko ; Halonen, Kari A I

Author_Institution

Electron. Circuits Design Lab., Helsinki Univ. of Technol., Espoo, Finland

Volume

36

Issue

1

fYear

2001

fDate

1/1/2001 12:00:00 AM

Firstpage

129

Lastpage

134

Abstract

A 9-bit 1.0-V pipelined analog-to-digital converter has been designed using the switched-opamp technique. The developed low-voltage circuit blocks are a multiplying analog-to-digital converter (MADC), an improved common-mode feedback circuit for a switched opamp, and a fully differential comparator. The input signal for the converter is brought in using a novel passive interface circuit. The prototype chip, implemented in a 0.5-μm CMOS technology, has differential nonlinearity and integral nonlinearity of 0.6 and 0.9 LSB, respectively, and achieves 50.0-dB SNDR at 5-MHz clock rate. As the supply voltage is raised to 1.5 V, the clock frequency can be increased to 14 MHz. The power consumption from a 1.0-V supply is 1.6 mW

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit feedback; comparators (circuits); low-power electronics; operational amplifiers; pipeline processing; switched networks; 0.5 micron; 1 V; 1.6 mW; 5 MHz; 9 bit; CMOS technology; common-mode feedback circuit; differential nonlinearity; fully differential comparator; integral nonlinearity; low-voltage circuit; multiplying analog-to-digital converter; passive interface circuit; pipelined switched-opamp ADC; Analog circuits; Analog-digital conversion; CMOS technology; Clocks; Feedback circuits; Frequency; Switches; Switching circuits; System-on-a-chip; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.896237

Filename

896237