Monitoring multistage integrated circuit fabrication processes

Author

Rao, Suraj ; Strojwas, Andrzej J. ; Lehoczky, J.P. ; Schervish, M.J.

Author_Institution

Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA

Volume

9

Issue

4

fYear

1996

fDate

11/1/1996 12:00:00 AM

Firstpage

495

Lastpage

505

Abstract

This paper presents a process monitoring system, which is designed to be used for monitoring VLSIC and other multistage manufacturing processes. The proposed process monitor can 1) simultaneously detect a variety of out-of-control conditions, 2) quantify the magnitude of process change, and 3) be used to compute the probability of meeting specifications. Average run length simulations show that for a single-stage process, the monitor is at least as good as the Shewhart-CUSUM charts for detecting changes in the distribution of the monitored characteristics. For a multistage process, however, the Bayesian monitor can significantly reduce the detection time by using in-line correlation information from earlier stages. The monitor has been applied to data from a state-of-the-art fabrication facility, and the results are promising

Keywords

Bayes methods; VLSI; integrated circuit technology; semiconductor process modelling; Bayesian monitor; VLSIC; in-line correlation; integrated circuit fabrication; multistage manufacturing; process monitoring; simulation; Bayesian methods; Circuits; Computational modeling; Condition monitoring; Control charts; Covariance matrix; Fabrication; Manufacturing processes; Observability; Process control;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.542165

Filename

542165