Abstract :
Improvements in computer store cycle and computing times have called for an increase in the rate of transfer of information beween the computer and its peripheral devices. This paper describes a system which can control the simultaneous demands of a number of transferring peripheral devices, to make up for the large differential between the information transfer rates of modern computer stores and existing peripheral devices. The system can control the transfer of information between 64 transferring peripheral devices, where the individual character transfer rate does not exceed 2.5kc/s, and a main store whose cycle time is 6¿s. The system has been designed to minimise the amount of buffer storage, between each peripheral device and the main store, without limiting the variety of peripheral operations. The paper also describes how this system has been extended to control a smaller number of simultaneously transferring high-transfer-rate devices, where the combined character rate does not exceed 1.2 Mc/s. The peripheral transfer control works in conjunction with a fixed, or director, programme which enables the peripheral devices to be divided amongst several time-shared programmes.
