Title :
100 MHz all-digital delay-locked loop for low power application
Author :
Kim, Bum-Sik ; Kim, Lee-Sup
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
fDate :
9/3/1998 12:00:00 AM
Abstract :
An all-digital delay-locked loop (AD-DLL) is proposed for low power application. The AD-DLL saves design time and effort for synthesis. The number of transistors is reduced by 50%, by introducing a dual-clock dual-input data flip-flop and a coarse delay time buffer. The lock indicator enables zero jitter
Keywords :
CMOS digital integrated circuits; delay circuits; flip-flops; 100 MHz; CMOS IC; coarse delay time buffer; digital DLL; digital delay-locked loop; dual-clock flip-flop; dual-input data flip-flop; lock indicator; low power application; zero jitter;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19981242
