Title :
A 2-GHz 1.6-mW phase-locked loop
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
fDate :
5/1/1997 12:00:00 AM
Abstract :
This paper describes the design of a 2 GHz 1.6 mW phase-locked loop (PLL) fabricated in an 18 GHz 0.6 μm BiCMOS technology. Employing cross-coupled delay elements and inductive peaking, the circuit merges the oscillator and the mixer into one stage to lower the power dissipation. An experimental prototype exhibits an r.m.s. jitter of 2.8 ps, a tracking range of 100 MHz, and a capture range of 70 MHz while operating from a 3 V supply. The phase noise in the locked condition is -115 dBc/Hz at 400 kHz offset
Keywords :
BiCMOS analogue integrated circuits; jitter; phase locked loops; phase noise; 0.6 micron; 1.6 mW; 18 GHz; 2 GHz; 3 V; BiCMOS technology; cross-coupled delay elements; inductive peaking; monolithic PLL; phase noise; phase-locked loop; power dissipation; BiCMOS integrated circuits; Delay; Frequency; Jitter; Phase locked loops; Phase noise; Power dissipation; Prototypes; Ring oscillators; Voltage-controlled oscillators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
